Voltage regulator stabilization for operation with a wide range of output capacitances

ABSTRACT

A voltage regulator includes a measurement circuit for obtaining a value representing a magnitude of an output capacitance connected at an output node of the voltage regulator. A correction circuit in the voltage regulator modifies a compensation circuit internal to the voltage regulator based on the value. The modification of the compensation circuit is done to ensure that sufficient stability margins to accommodate the output capacitance are ensured for the main feedback loop in the voltage regulator. In an embodiment, a voltage proportional to the output capacitance is detected at start-up of the voltage regulator, and a corresponding binary signal is generated. The logic value of the binary signal is used to add or remove components and/or circuit portions in the compensation circuit to ensure stability. The voltage regulator is thus designed to support a wide range of output capacitance values.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate generally to voltageregulators, and more specifically to techniques for stabilizing avoltage regulator for operation with a wide range of outputcapacitances.

2. Related Art

A voltage regulator receives an unregulated voltage as input andprovides a regulated voltage as output. For improving regulation, anoutput capacitor (not included in the voltage regulator) is usuallyconnected at the output node at which the voltage regulator generatesthe regulated output voltage. The specific value of the output capacitormay be different based on the requirements of the applicationenvironment. For example, if better regulation is required, the outputcapacitor may be chosen to have a larger capacitance value, andvice-versa. Thus, a voltage regulator may need to be designed to operatefor a wide range of output capacitance values.

As is well known in the relevant arts, a voltage regulator employsclosed-loop feedback, and stability of the closed-loop (or simply of thevoltage regulator) is typically required to be ensured. The capacitanceof the output capacitor forms a pole in the transfer function of theclosed-loop, and the specific value of the output capacitance generallyaffects the stability of the closed-loop.

Compensation circuits are generally implemented within a voltageregulator to make the closed-loop stable. Stability of the closed-loopdepends on the positions of all the poles and zeros in the closed-loop.The wide range of possible output capacitance values generallycomplicates the design of the compensation circuits within the voltageregulator, and may require trade-offs in the design of the voltageregulator. For example, one possible technique to ensure stability is todesign the voltage regulator to have a dominant internal pole(lowest-frequency pole in the loop due to circuits or componentsimplemented within the voltage regulator), thereby minimizing the effectof the pole due to the output capacitance on the loop stability.However, such an approach may reduce the bandwidth of the voltageregulator, thereby resulting in poor transient performance, and hencemay not be desirable at least for such reason.

Hence, it is generally desirable to design a voltage regulator such thatloop-stability is ensured for a wide range of possible outputcapacitance values.

SUMMARY

This Summary is provided to comply with 37 C.F.R. §1.73, requiring asummary of the invention briefly indicating the nature and substance ofthe invention. It is submitted with the understanding that it will notbe used to interpret or limit the scope or meaning of the claims.

A voltage regulator includes a measurement circuit and a correctioncircuit. The measurement circuit is designed to generate a valuerepresenting a magnitude of an output capacitance connected at an outputnode of the voltage regulator. The correction circuit is designed tomodify, based on the value generated by the measurement circuit, acompensation circuit internal to the voltage regulator.

Several embodiments of the present disclosure are described below withreference to examples for illustration. It should be understood thatnumerous specific details, relationships, and methods are set forth toprovide a full understanding of the embodiments. One skilled in therelevant art, however, will readily recognize that the techniques can bepracticed without one or more of the specific details, or with othermethods, etc.

BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS

Example embodiments will be described with reference to the accompanyingdrawings briefly described below.

FIG. 1 is a diagram of an example component in which several embodimentscan be implemented.

FIG. 2 is a diagram showing partial internal details of a low-dropoutregulator (LDO).

FIG. 3 is a diagram illustrating the details of a start-up circuit usedin a LDO, in an embodiment.

FIG. 4 is a diagram of the equivalent circuit of FIG. 3 during start-upof the LDO.

FIG. 5 is a diagram illustrating the manner in which a measurerepresenting output capacitance of a LDO is determined, in anembodiment.

FIG. 6 is a diagram illustrating the details of a circuit used forobtaining a measure representing the magnitude of output capacitance ofa LDO, in another embodiment.

FIG. 7 is a block diagram of partial internal details of a LDO in anembodiment, used to illustrate the manner in which a compensationcircuit implemented within the LDO is modified.

FIGS. 8A and 8B are diagrams showing gain-versus-frequency plots ofparallely-connected amplifier chains in an LDO, in an embodiment.

FIG. 9 is a block diagram of an example receiver system incorporating avoltage regulator, in an embodiment.

The drawing in which an element first appears is indicated by theleftmost digit(s) in the corresponding reference number.

DETAILED DESCRIPTION

Various embodiments are described below with several examples forillustration.

1. Voltage Regulator

FIG. 1 is a diagram of an example component in which several embodimentscan be implemented. FIG. 1 is shown containing low-dropout regulator(LDO) 150, battery 110, capacitor 120, and load 130. LDO 150, which is alinear regulator, receives the unregulated power supply voltage (Vbat)from battery 110 on input node 149, and provides a regulated outputvoltage on output node 151. Capacitor 120 is an output capacitor usedfor providing improved regulation, and has a value that may beapplication-specific. For example, the nature of load 130 and/or thelevel of regulation required may determine the value of the capacitanceof capacitor 120. Thus, depending on the specific applicationrequirements, the possible range for the selected value of capacitance120 that LDO 150 may need to operate with may be wide. Terminal 199represents a ground terminal. While the description below is providewith respect to linear voltage regulators, the techniques describedherein can be applied in switching regulators as well.

FIG. 2 shows partial internal details of LDO 150. The details are shownmerely to illustrate the effect of output capacitance on loop stability,and the actual implementation may be different and/or contain morecircuits and corresponding interconnections. Output capacitor 120 isalso shown in FIG. 2. Output 212 of amplifier 210 controls theresistance of pass transistor 220 to maintain node 151 at a desiredconstant voltage (regulated voltage). Resistor 230 (first resistor) and240 (second resistor) implement a voltage divider network, and thevoltage at node 234 is fed back to the non-inverting input (+) ofamplifier 210, which is shown implemented as an operational amplifier(OPAMP). Amplifier 210 receives, on its inverting (−) terminal, areference voltage from voltage reference 250 on path 251. Voltagereference 250 may be implemented, for example, as a band-gap reference.Amplifier 210 generates an output voltage on path 212 (connected to thegate terminal of pass transistor 220) so as to maintain the voltage atnode 251 equal to the voltage at node 234. The connection of node 234back to amplifier 210 implements a closed-loop feedback for regulatingoutput voltage 151. This closed-loop is referred to herein as the mainfeedback loop in LDO 150 to distinguish this loop from other feedbackloops, such as a Miller feedback loop (which may be used to providecompensation), that may also be contained within LDO 150.

As noted above, the presence of capacitor 120 creates a pole in thetransfer function of the main feedback loop. Different capacitancevalues of capacitor 120 translate to different pole locations due to theoutput capacitor, which in turn may render design of compensationschemes for loop stability of the main feedback loop complicated.

In embodiments of the present disclosure, the value of the outputcapacitance is measured, or some parameter representing (or proportionalto) the output capacitance is determined. Depending on the value thusmeasured, one or more parameters of a compensation circuit implementedwithin LDO 150 is/are adjusted, or the compensation circuit is somehowmodified such that loop stability of the main feedback loop is ensured.Such measurement and adjustment/modification is performed automaticallyby corresponding circuits implemented within LDO 150, as described withexamples below.

2. Measuring Output Capacitance

In an embodiment, LDO 150 is implemented with circuitry to cause outputvoltage 151 to ramp-up (increase from zero to some desired value) with aconstant slope upon power-ON of LDO 150, a brief description of which isprovided below. However, for further details, the reader is referred toU.S. patent application Ser. No. 12/649,035, titled “STARTUP CIRCUIT FORAN LDO”, filed on 29 Dec., 2009, which is incorporated by reference inits entirety herewith.

FIG. 3 is a diagram showing output capacitor 120 and partial internaldetails of LDO 150. In addition to amplifier 210, pass-transistor 220,resistor 230 and 240, and voltage reference 250, LDO 150 is also showncontaining switches 331 (S1), 332 (S2) and 333 (S3), capacitor 310(Cint), current source 320 and comparator 380. Each of switches S1, S2and S3 may be implemented using transistors, with corresponding controlsignals for opening and closing the corresponding switches beinggenerated by suitable logic, not shown.

The non-inverting (+) terminal of amplifier 210 is connectable to node234 via switch 331(S1). Node 312 is connectable to voltage 251 viaswitch S3. The non-inverting (+) terminal of amplifier 210 isconnectable to voltage 251 via switches S2 and S3. Block 350 is referredto herein as a start-up circuit.

Immediately on power-ON of LDO 150 (for example, on connecting battery110 to LDO 150, or when amplifier 210 and voltage reference 250 areenabled for operation via signal EN (390), switches S3 and S2 areclosed. Both the inverting and non-inverting terminals of amplifier 210are at the same voltage (equal to the voltage at node 251, also referredherein as Vbg). The voltage at output node 151 is 0 volts (V) since LDO150 is in a disabled state prior to power-ON or enabling (output voltage151 is typically discharged to ground (0V) through internal or parasiticpaths when LDO 150 is disabled). Capacitor Cint charges to a voltageequal to that at node 251, with the polarity of the voltage (Vbg) acrossCint being as shown in FIG. 3.

Switch S3 is subsequently opened, with switch S1 remaining open andswitch S2 remaining closed. With these conditions, the circuit of FIG. 3reduces to the equivalent circuit of FIG. 4. Capacitor 310 startsdischarging the stored charge. Current source 320 causes capacitor 310to discharge with a constant current. Assuming the constant currentvalue through current source 320 is ‘I320’, the rate of change ofvoltage (dv/dt) at node 151 is expressed by the following equation:

dv/dt=C310/I320  Equation 1

wherein,

C310 is the capacitance of capacitor 310.

From equation 1, it may be observed that the value of dv/dt is aconstant, i.e., the output voltage at node 151 changes at a constantrate. Start-up circuit 350 therefore enables output voltage 151 toramp-up at a constant rate.

Ramp-rate (dv/dt) is also independent of the output capacitor 120. Sincethe ramp-rate (dv/dt) of the output voltage (at node 151) is a constantthat is set by design internally in LDO 150, the current through outputcapacitor 120 can be used as an indicator of the magnitude of outputcapacitance.

A rate of change of voltage of dv/dt at node 151 results in a currentI120 through output capacitor 120 as given by the following equation:

I120=C120/[dv/dt]  Equation 2

wherein,

C120 is the capacitance of capacitor 120, and

dv/dt is as specified in equation 1, and

I120 is the current through output capacitor 120.

It may be appreciated that, dv/dt being a constant, I120 varies onlywith C120, and may therefore be used as an indicator of the magnitude ofC120. Current I120 also equals the current through pass transistor 220.

Once output voltage 151 reaches a desired nominal value, current source320 is switched-off. The switching-off of current source 320 is effectedby signal 381 generated by comparator 380. When the voltage at node 234becomes greater than the voltage at node 312, comparator 380switches-off current source 320, and LDO 150 then operates normally togenerate a regulated voltage at node 151. The interval between the timeinstances at which LDO is enabled for operation (or from the instant ofapplication of Vbat 110) and the switching-off of current source 320 isreferred to herein as a ‘start-up interval’, and the current flowingthrough LDO 150 (i.e., current between nodes 149 and 151 shown in FIG.1, also equal to I120 of Equation 2) is referred to as the ‘start-upcurrent’.

FIG. 5 is another diagram showing partial internal details of LDO 150,and illustrating the manner in which a measure representing outputcapacitance (i.e., of capacitor 120) is determined. In addition to passtransistor 220, start-up circuit 350 and output capacitor 120,comparator 530, transistor 510, resistor 520 and logic 540 are alsoshown contained in LDO 150.

The gate terminal of mirror transistor 510 is also connected to node 212(output of amplifier 210 of FIG. 4). Hence, transistors 510 and 220 forma current-mirror pair. The dimensions (channel width, etc) of transistor510 may be sized to be equal or some other ratio of the dimensions oftransistor 220. The current through transistor 510, and therefore thecurrent through resistor 520 is either equal to or a known fraction ofI120 (the current that flows through pass transistor 220 duringstart-up). Thus the voltage drop across resistor 520, i.e., the voltageat node 531, is indicative of and proportional to C120.

Comparator 530 receives the voltage across resistor 520 on its invertingnode (531) and a reference voltage on its non-inverting terminal (532),and generates binary output 534 representing the result of thecomparison. Logic 540 forwards binary output 534 on path 541 if signal551 from start-up circuit 350 indicates that the start-up phase iscomplete and that LDO 150 is operating in normal mode to generate aregulated output voltage 151. Signal 551 may be the same as signal 381(FIG. 4), or may be generated in some other known way. A compensationcircuit implemented within LDO 150 may be adjusted or modified based onthe value of binary signal 541, as illustrated with examples below.While a simple binary (two-level) comparison is shown in FIG. 5, inother embodiments voltage 531 may be compared with multiple ranges ofvoltages, using multiple comparators to generate corresponding multipleoutputs. Thus, multiple ‘levels’ of adjustments or modifications of thecompensation circuit (corresponding to multiple ranges of outputcapacitance) are also possible. The circuit formed by transistor 510,resistor 520, and comparator 530 may be viewed as a “measurementcircuit” operating to generate a value (logic level of binary signal534) representing output capacitance 120.

FIG. 6 is a diagram illustrating the details of a circuit used forobtaining a measure representing the magnitude of output capacitance inanother embodiment of LDO 150. Transistor 610 is a mirror of passtransistor 220 (not shown in FIG. 6), and shares the same source andgate connections as pass transistor 220. Hence, the current flowingthrough transistor 610 is a fixed fraction of the output current flowingthrough pass transistor 220, and flows through resistor 630 andtransistor 620. Transistors 620 and 630 form a cascoded pair. The gateof transistor 620 receives a reference voltage on path 621. The voltageacross resistor 630 is sensed by comparator 660, whose output 661 may beprovided as input to inverting terminal (−) of comparator 530 shown inFIG. 5, with output 534 of comparator 530 disconnected from logic 540.Comparator 530 and logic 540 of FIG. 5 process their respective inputsas described above with respect to FIG. 5, and generate signal 541.Alternatively, multiple outputs, each indicating a corresponding valueor range of values of output capacitor 120 may also be generated, aswould be apparent to one skilled in the relevant arts, and also notedabove. Similar to the measurement circuit noted above with respect toFIG. 5, transistors 610 and 620, resistor 630 and comparator 660 of FIG.6 in combination with comparator 530 of FIG. 5 may also be viewed as a“measurement circuit”.

The logic level of signal 534 indicates whether the load current, andhence the output capacitance, is above or below a certain threshold, andis thus representative of the value of the output capacitance. A desiredvalue of the threshold may be determined a priori based on stabilityanalysis of the main feedback loop of LDO 150 for various values ofoutput capacitances, and the value of the reference voltage on path 532may be set accordingly. Output 541 is used to adjust or modify thecompensation circuit appropriately, as described next.

3. Modifying the Compensation Circuit

FIG. 7 is a block diagram of partial internal details of LDO 150, in anembodiment. Amplifiers 705-1 through 705-N represent cascaded amplifierstages. Similarly, amplifiers 710-1 through 710-N represent cascadedamplifier stages. The output of amplifier 705-N (first amplifier) isconnected to the input of gate driver stage 709. Blocks 705-1 to 705-N,710-1 to 710-N together with gate driver stage 709 represent amplifier210 of FIG. 2. The voltage on node 707 is a “correction voltage”generated based on the difference between the voltage at node 234 andthe output voltage of voltage reference 250.

Amplifier 710-N is selectively connectable to the input of gate driverstage 709, as described below. Transistor 740 is a pass-transistor whoseresistance is controlled to generate a regulated voltage at output 151.Transistor 745 together with pass-transistor 740 forms a cascoded pair,and the cascoded pair is equivalent in function to pass-transistor 220of FIG. 4. Transistors 750 (mirror-transistor) and 755 form a cascodedpair, and are a mirror of the pair formed by transistors 740 and 745.The circuits of FIGS. 3 and 5 (or alternatively FIGS. 3 and 6), and thecorresponding interconnections, are not shown in FIG. 7, but are assumedto be included in LDO 150 shown in FIG. 7.

The tap from node 234 to the non-inverting (+) input of amplifier 705-1(as well as 710-1) represents the feedback path of the main feedbackloop that operates to regulate output voltage 151. The path from node776 (or 761 depending on which of switches 770 and 775 is closed) viacapacitor 783 to node 706 (feedback terminal) of amplifier 705-Nrepresents a feedback path for Miller loop compensation.

The value of capacitance in the feedback path for Miller loopcompensation (Miller compensation loop or Miller feedback loop) istermed Miller capacitance, and equals either the capacitance ofcapacitor 783 (first Miller capacitor) alone, or the sum of capacitancesof capacitors 783 and 782 (second Miller capacitor), depending onwhether switch 781 is closed or not. The RC circuit formed by the seriesconnection of resistor 715 and capacitor 720 is used to generate a pole(internal pole) in the main feedback loop of LDO 150. The internal polethus generated assists in ensuring stability of the feedback-loop. Anadditional RC circuit formed by the series connection of resistor 725and capacitor 730 may be connected by closing switch 735, as describedbelow.

Components 715, 720, 735, 725, 730, 781, 782, 783, 784, 785, 786, 780,770, 775, 765, and 760 are used to provide compensation for stabilizingLDO 150, and are referred to herein as a compensation circuit. Thecompensation circuit is implemented within LDO 150.

In an embodiment, if capacitance (C120) of output capacitor 120 ishigher than a threshold as indicated by signal 541, switch 775 is closedand switch 770 (second switch) is opened. However, if capacitance ofoutput capacitor 120 is less than the threshold (as indicated by signal541), switch 770 is closed and switch 775 is opened. With switch 775(first switch) closed, the tap point of the Miller feedback loop (viacapacitor 783) is at node 776 (first junction node). Resistance R765(fifth resistance) of resistor 765 represents the sum of parasiticresistance (of bond wire from internal pad to integrated circuit (IC)pin representing terminal 151) and equivalent series resistance (ESR) ofcapacitor 120. Resistance 765 in combination with C120 form a zero inthe closed-loop transfer function of the main feedback loop of LDO 150,the zero being located at the frequency [1/(2π(R765)(C120))]. When C120is higher than the threshold noted above, the location of the zero is ata desired frequency. However, when C120 is less than the threshold, thelowering of the location of the zero is such as to render the mainfeedback loop potentially unstable (insufficient gain and/or phasemargins). Therefore, when C120 is less than the threshold, the tap pointis changed to node 761 (second junction node). Therefore, the locationof the zero is changed to a frequency specified by [1/(2π(R760)(C120))],wherein R760 is the resistance of resistor 760 (third resistor). R760 isdesigned to have a larger value than R765. As a result, the zerolocation can be maintained at a desired frequency despite the reductionin C120.

In changing the tap point from node 776 to node 761, the tap point ofMiller capacitor 783 is also changed to a higher-resistance tap (higherresistance due to R760 being greater than R765). At higher frequencies,the path through capacitor 780 dominates the path through resistors 765and 230. As a result, the change in the tap point changes the zerofrequency for the main feedback loop as well, and consequently variationin the zero frequency due to changes in the value of output capacitanceis reduced. Thus, on detecting that the output capacitance is lower thanthe threshold, the effective ESR is increased (by turning switch 770 ONand switch 775 OFF) so that the increased value of resistance (R760rather than R765) can compensate for the decreased output capacitance tosome extent.

In another embodiment, in which the pole due to C120 is the dominantpole (i.e., pole due to C120 is at a lower frequency than any internalpole (including the pole due to RC circuit formed by resistor 715 andcapacitor 720), if C120 is lower than the predetermined threshold notedabove, the Miller capacitance is increased. Switch 781 (third switch) isclosed, and the Miller capacitance is the sum of capacitances ofcapacitors 783 and 782. The value of the Miller capacitance is therebyincreased. As a result, the pole due to C120 is ‘pushed’ further in(i.e., the location of the pole due to C120 is moved to a lowerfrequency than otherwise), and the location of internal poles are pushedto higher frequencies. As a result, the bandwidth of the main feedbackloop is reduced, and stability is ensured. On the other hand, if C120 ishigher than the threshold, switch 781 is opened, and the Millercapacitance is smaller (being the capacitance of capacitor 783 alone).

In yet another embodiment, in which an internal pole (e.g., the pole dueto the RC network (first RC network) formed by resistor 715 andcapacitor 720) is the dominant pole (i.e., internal pole is at a lowerfrequency than the pole due to C120), if C120 is lower than thethreshold, switch 735 is closed. As a result, the frequency of thedominant (internal) pole is decreased due to the connection of the RCnetwork (second RC network) formed by resistor 725 and capacitor 730.The decrease in the frequency of the internal pole reduces the bandwidthof the main feedback loop, thereby ensuring loop stability. If C120 ishigher than the threshold, switch 735 is left open. Capacitance 730 isimplemented to be greater than capacitance 720.

In some LDO architectures (i.e., in some embodiments of LDO 150), thepole (output pole) due to output capacitor 120 may be the dominant poleif the output capacitance is large, the output pole becoming anon-dominant pole if the output capacitance is small. In sucharchitectures, when the output capacitance is small, one technique tocancel the non-dominant output pole is to generate a zero at thefrequency of the output pole. Connecting two amplifiers in parallel, onewith high gain and low bandwidth and the other with low gain and highbandwidth is one way of generating such a zero. Accordingly, in some ofsuch embodiments, if C120 is lower than the threshold, each of switches784 (fifth switch) and 786 (sixth switch) is closed, thereby connectingthe cascaded amplifiers 710-1 through 710-N in parallel with thecascaded amplifiers 705-1 through 705-N. Specifically, the output ofamplifier 710-N is connected to the input of gate driver stage 709, andresistor 785 (fourth resistor) is connected between the input of gatedriver stage 709 and ground. The total gain provided by cascadedamplifiers 705-1 through 705-N (referred to conveniently as cascade-1)is designed to be high. By comparison, the total gain provided bycascaded amplifiers 710-1 through 710-N (referred to conveniently ascascade-2) is comparatively lower, but has a wider bandwidth than thatprovided by cascade-1. Plots S1 and S2 of FIG. 8A are examplegain-versus-frequency plots of cascade-1 (first cascade of amplifiers)and cascade-2 (second cascade of amplifiers) respectively. Frequenciesf1 and f3 are respective pole frequencies of cascade-1 and cascade-2.Frequency f2 is the intersection point of plots S1 and S2. FIG. 8A is again-versus-frequency plot of the sum of S1 and S2. It may be observedthat the connection of cascade-2 in parallel with cascade-1 generates azero at frequency f2.

Based on the specifics of the design of LDO 150 and expected range ofpossible values of output capacitance, the techniques noted above formodifying the compensation circuit can either be applied independentlyof each other, or two or more of the techniques can be applied incombination. Thus, circuits within LDO 150 measure output capacitance,or a parameter representative of the output capacitance, and modify thecompensation circuit implemented within LDO 150 according to themeasurement. Depending on which of the techniques for modifying thecompensation circuit is/are implemented, the logic level of signal 541(shown in FIG. 5) controls the state (whether open or closed) of thecorresponding switch(s). Thus, for example, when the Miller capacitanceis to be selected to either equal the capacitance of capacitor 783 aloneor the sum of capacitances of capacitors 783 and 782, signal 541controls the desired state (open/closed) of switch 781. The combinationof logic 540 and the corresponding switch (or switches) 770, 775, 781,735, 784 and 786 represents a “correction circuit” that operates tomodify the compensation circuit, based on the output of the “measurementcircuit” noted above.

4. Example System

FIG. 9 is a block diagram of an example receiver system 900. Receiversystem 900 may correspond to receivers such as a Global PositioningSystem (GPS) receiver, communication receivers such as an FM (frequencymodulation) receiver, etc. Receiver system 900 is shown containingantenna 901, analog processor 920, ADC 950, processing unit 990 andvoltage regulator 150, battery 110 and output capacitor 120.

Antenna 901 may receive various signals transmitted on a wirelessmedium. The received signals may be provided to analog processor 920 onpath 912 for further processing. Analog processor 920 may perform taskssuch as amplification (or attenuation as desired), filtering, frequencyconversion, etc., on the received signals and provides the resultingprocessed signal on path 925.

ADC 950 converts the analog signal received on path 925 to correspondingdigital values, which are provided on path 959 for further processing.ADC 950 may be implemented as a SD ADC according to techniques describedin detail above. Processing unit 990 receives the data values on path959, and processes the data values to provide various user applications.Voltage regulator 150 provides a regulated voltage (with battery 110being the power source) for the operation of each of analog processor920, ADC 950, and processing unit 990. Voltage regulator 150 operates tomodify its internal compensation circuitry based on a measurement ofcapacitance 120, as described in detail above.

While in the illustrations of FIGS. 1, 2, 3, 4, 5, 6 and 7, althoughterminals/nodes are shown with direct connections to (i.e., “connectedto”) various other terminals, it should be appreciated that additionalcomponents (as suited for the specific environment) may also be presentin the path, and accordingly the connections may be viewed as being“electrically coupled” to the same connected terminals. In the instantapplication, power supply and ground terminals are referred to asconstant reference potentials.

While various embodiments of the present disclosure have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. Thus, the breadth and scope of thepresent disclosure should not be limited by any of the above-describedembodiments, but should be defined only in accordance with the followingclaims and their equivalents.

What is claimed is:
 1. A voltage regulator comprising: a measurementcircuit for generating a value representing a magnitude of an outputcapacitance connected at an output node of the voltage regulator; and acorrection circuit for modifying, based on the value, a compensationcircuit internal to the voltage regulator.
 2. The voltage regulator ofclaim 1, further comprising a start-up circuit designed to generate, ina start-up interval, an output voltage with a constant ramp-rate at theoutput node, wherein the measurement circuit generates a voltageproportional to a start-up current drawn via the voltage regulator inthe start-up interval, wherein the measurement circuit compares thevoltage with a reference voltage to generate the value.
 3. The voltageregulator of claim 2, wherein the value representing the magnitude ofthe output capacitance is a binary signal, a first logic level of thebinary signal corresponding to a magnitude of the output capacitanceless than a threshold, and a second logic level of the binary signalcorresponding to the magnitude of the output capacitance greater thanthe threshold, wherein the voltage regulator comprises a pass-transistorcoupled in series with a voltage divider network containing a firstresistor and second resistor, the voltage divider network being coupledin parallel with the output capacitor, wherein a path coupling thepass-transistor with the voltage divider network is associated with afifth resistance, wherein a tap point of the voltage divider network iscoupled to a first amplifier coupled to the pass-transistor to form afeedback path of a main feedback loop of the voltage regulator, whereinthe first amplifier is comprised in a first cascade of amplifiers,wherein an output of the first cascade of amplifiers is coupled to thepass-transistor, the first cascade of amplifiers to amplify a differenceof a reference voltage and a voltage at the junction of the firstresistor and the second resistor, and to generate a correction voltageat an output node of the first amplifier, wherein the output of thefirst cascade of amplifiers is generated as a difference of a voltage atthe tap point and the reference voltage.
 4. The voltage regulator ofclaim 3, wherein the compensation circuit comprises: a Miller feedbackloop, the Miller feedback loop comprising a first Miller capacitor,wherein a first terminal of the first Miller capacitor is coupled to afeedback terminal of the first amplifier in the first cascade ofamplifiers; and a mirror-transistor mirroring the pass transistor, themirror-transistor coupled to the output node via a third resistor; afirst switch and a second switch, wherein if the binary signal has thesecond logic level, the correction circuit opens the second switch andcloses the first switch to connect the second terminal of the firstMiller capacitor to a first junction node via which the fifth resistanceis coupled to the pass-transistor, wherein if the binary signal has thefirst logic level, the correction circuit opens the first switch andcloses the second switch to connect the second terminal of the firstMiller capacitor to a second junction node via which the third resistoris coupled to the mirror-transistor.
 5. The voltage regulator of claim4, wherein the compensation circuit further comprises a second Millercapacitor coupled in series with a third switch, the series connectionof the second Miller capacitor and the third switch being coupled inparallel with the first Miller capacitance, wherein if the binary signalhas the first logic level, the correction circuit closes the thirdswitch to couple the second Miller capacitor and the first Millercapacitor in parallel, wherein if the binary signal has the second logiclevel, the correction circuit opens the third switch.
 6. The voltageregulator of claim 4, wherein the compensation circuit furthercomprises: a first series RC network comprising a resistor and acapacitor coupled in series, the first RC network being coupled betweenthe output node of the first amplifier and a constant referencepotential; and a second series RC network comprising a resistor and acapacitor; and a fourth switch, wherein if the binary signal has thefirst logic level, the correction circuit closes the fourth switch tocouple the second series RC network in parallel with the first series RCnetwork, wherein if the binary signal has the second logic level, thecorrection circuit opens the fourth switch.
 7. The voltage regulator ofclaim 4, further comprising a second cascade of amplifiers to amplifythe difference of the reference voltage and the voltage at the junctionof the first resistor and the second resistor, wherein the compensationcircuit further comprises: a fifth switch; a sixth switch; and a fourthresistor, wherein the fifth switch, the sixth switch and the fourthresistor are coupled in series, wherein if the binary signal has thefirst logic level, the correction circuit closes each of the fifthswitch and the sixth switch to couple an output node of the secondcascade of amplifiers to the output node of the first amplifier, and thefourth resistor between the output node of the first amplifier and theconstant reference potential, wherein if the binary signal has thesecond logic level, the correction circuit opens the fifth switch andthe sixth switch.
 8. The voltage regulator of claim 1, wherein thevoltage regulator is a low-dropout regulator (LDO).
 9. The voltageregulator of claim 2, wherein the voltage divider network is comprisedin the start-up circuit, the start-up circuit further comprising: aseries connection of a capacitor and a constant current source, theseries connection coupled between the output node and the constantreference potential; and a comparator, a first input of the comparatorcoupled to a junction of the first resistor and the second resistor, asecond input of the comparator coupled to a junction of the capacitorand the current source, wherein, in the start-up interval, the capacitoris charged to the reference voltage such that voltage across thejunction of the capacitor and the current source and the output nodeequals +Vbg, wherein Vbg is the reference voltage, wherein the capacitoris then allowed to discharge through the constant current source,whereby the output voltage in the start-up interval is generated to havethe constant ramp-rate.
 10. A system comprising: an antenna to receive asignal on a wireless medium; an analog processor to process the signaland to generate a processed signal; an analog to digital converter (ADC)to receive the processed signal as input and to generate a plurality ofdigital values representing the processed signal; a processor to processthe plurality of digital values; and a voltage regulator to receivepower from a battery, and provide a regulated output voltage for theoperation of each of the analog processor, ADC, and the processor,wherein, the voltage regulator comprises: a measurement circuit forgenerating a value representing a magnitude of an output capacitanceconnected at an output node of the voltage regulator; and a correctioncircuit for modifying, based on the value, a compensation circuitinternal to the voltage regulator.
 11. The system of claim 10, whereinthe value representing the magnitude of the output capacitance is abinary signal, a first logic level of the binary signal corresponding toa magnitude of the output capacitance less than a threshold, and asecond logic level of the binary signal corresponding to the magnitudeof the output capacitance greater than the threshold, wherein thevoltage regulator comprises a pass-transistor coupled in series with avoltage divider network containing a first resistor and second resistor,the voltage divider network being coupled in parallel with the outputcapacitor, wherein a path coupling the pass-transistor with the voltagedivider network is associated with a fifth resistance, wherein a tappoint of the voltage divider network is coupled to a first amplifiercoupled to the pass-transistor to form a feedback path of a mainfeedback loop of the voltage regulator, wherein the first amplifier iscomprised in a first cascade of amplifiers, wherein an output of thefirst cascade of amplifiers is coupled to the pass-transistor, the firstcascade of amplifiers to amplify a difference of a reference voltage anda voltage at the junction of the first resistor and the second resistor,and to generate a correction voltage at an output node of the firstamplifier, wherein the output of the first cascade of amplifiers isgenerated as a difference of a voltage at the tap point and thereference voltage.
 12. The system of claim 11, wherein the voltageregulator further comprises a start-up circuit designed to generate, ina start-up interval, an output voltage with a constant ramp-rate at theoutput node, wherein the measurement circuit generates a voltageproportional to a start-up current drawn via the voltage regulator inthe start-up interval, wherein the measurement circuit compares thevoltage with a reference voltage to generate the value.
 13. The systemof claim 12, wherein the compensation circuit comprises: a Millerfeedback loop, the Miller feedback loop comprising a first Millercapacitor, wherein a first terminal of the first Miller capacitor iscoupled to a feedback terminal of the first amplifier in the firstcascade of amplifiers; and a mirror-transistor mirroring the passtransistor, the mirror-transistor coupled to the output node via a thirdresistor; a first switch and a second switch, wherein if the binarysignal has the second logic level, the correction circuit opens thesecond switch and closes the first switch to connect the second terminalof the first Miller capacitor to a first junction node via which thefifth resistance is coupled to the pass-transistor, wherein if thebinary signal has the first logic level, the correction circuit opensthe first switch and closes the second switch to connect the secondterminal of the first Miller capacitor to a second junction node viawhich the third resistor is coupled to the mirror-transistor.
 14. Thesystem of claim 13, wherein the compensation circuit further comprises asecond Miller capacitor coupled in series with a third switch, theseries connection of the second Miller capacitor and the third switchbeing coupled in parallel with the first Miller capacitance, wherein ifthe binary signal has the first logic level, the correction circuitcloses the third switch to couple the second Miller capacitor and thefirst Miller capacitor in parallel, wherein if the binary signal has thesecond logic level, the correction circuit opens the third switch. 15.The system of claim 14, wherein the compensation circuit furthercomprises: a first series RC network comprising a resistor and acapacitor coupled in series, the first RC network being coupled betweenthe output node of the first amplifier and a constant referencepotential; and a second series RC network comprising a resistor and acapacitor; and a fourth switch, wherein if the binary signal has thefirst logic level, the correction circuit closes the fourth switch tocouple the second series RC network in parallel with the first series RCnetwork, wherein if the binary signal has the second logic level, thecorrection circuit opens the fourth switch.
 16. The system of claim 15,further comprising a second cascade of amplifiers to amplify thedifference of the reference voltage and the voltage at the junction ofthe first resistor and the second resistor, wherein the compensationcircuit further comprises: a fifth switch; a sixth switch; and a fourthresistor, wherein the fifth switch, the sixth switch and the fourthresistor are coupled in series, wherein if the binary signal has thefirst logic level, the correction circuit closes each of the fifthswitch and the sixth switch to couple an output node of the secondcascade of amplifiers to the output node of the first amplifier, and thefourth resistor between the output node of the first amplifier and theconstant reference potential, wherein if the binary signal has thesecond logic level, the correction circuit opens the fifth switch andthe sixth switch.
 17. The system of claim 10, wherein the voltageregulator is a low-dropout regulator (LDO).